VLSI Defense & EDA Glossary

The graphical user interface in Cadence Virtuoso used to configure simulation models, analyses (transient, DC, AC), design variables, corners, and output expressions.

The Antigravity CLI and agent runtime developed by Google DeepMind for advanced agentic pair-programming and multi-agent coordination.

Cadence standard primitive component library containing ideal electrical elements such as independent sources (vpulse, vdc), ground symbols (gnd!), and ideal passive resistors (res) and capacitors (cap).

Plasma-induced gate oxide damage occurring during reactive ion etching when long, unconnected metal interconnect lines accumulate charge that discharges through thin transistor gate oxides.

The ratio of channel width to channel length in a MOSFET, governing current drive capacity ($I_{ds} \propto W/L$), transconductance ($g_m$), and parasitic gate capacitance.

Cadence physical verification suite performing Design Rule Checking (DRC), Layout Versus Schematic (LVS), and Parasitic Extraction (RCX) on IC layouts.

A frozen, verified state of repository files, netlists, reports, and VM images that serves as an authoritative reference point for future work.

A steady DC control potential applied to the gate of an MOS transistor to set its quiescent gate-to-source bias ($V_{gs}$) and determine its operating current.

The shift in a MOSFET's threshold voltage ($V_{th}$) caused by a non-zero voltage difference between source and substrate ($V_{sb} > 0$), widening the depletion region.

The industry-standard electronic design automation (EDA) software platform by Cadence Design Systems for schematic entry, layout editing, and mixed-signal IC design.

A headless 32-bit CentOS 6.5 VirtualBox guest machine used to host the Cadence IC615, Spectre 12.1, and Assura 4.1 software suite.

Cadence proprietary data structure that defines component parameters, simulation models, terminal labels, and callback procedures for Virtuoso library cells.

The shortening of the effective inverted channel length in a MOSFET as drain-to-source voltage ($V_{ds}$) increases beyond pinch-off, causing a finite output conductance $g_{ds}$.

The effective electrical resistance between drain and source terminals of an MOS transistor operating in the deep linear (triode) conduction region: $R_{on} \approx [\mu C_{ox} (W/L) (V_{gs} - V_{th})]^{-1}$.

The Cadence automated grid-based and shape-based interconnect router used to execute global, track, and detail routing passes on physical layouts.

The primary control and console logging window of Cadence Virtuoso where user commands, SKILL expressions, load logs, and tool error messages are output.

Complementary differential clock signals where CKb is 180° out of phase with CK, providing non-overlapping control for sampling and regeneration phases.

An institutional ledger recording every numerical assertion and benchmark in a manuscript draft, linking each claim to an evidentiary simulation file and audit verdict.

Integrated circuit technology combining both n-type (NMOS) and p-type (PMOS) field-effect transistors on a single silicon substrate to achieve high noise immunity and low static power.

A concise peer-reviewed paper documenting where a published circuit design equation breaks down under advanced process nodes, providing a revised physical model and measured data.

The longest sequence of dependent tasks that dictates the minimum calendar duration required to complete an engineering project milestone.

Two active transistors where the drain of each is cross-connected to the gate of the other, forming a regenerative positive feedback loop with high differential negative resistance.

The high-speed sized frequency divider variant designed to maximize operating frequency and achieve benchmark phase accuracy near its speed limit.

The nominal sized frequency divider variant designed for operation at the reference paper's input clock frequency of 1.4 GHz.

Cadence executable that converts a Design Framework II (DFII) schematic view into a Volume Layout Database (VLDB) netlist file required by Assura LVS.

A symmetrical two-transistor circuit topology that amplifies differential input voltage signals while rejecting common-mode noise and power supply fluctuations.

Geometric layout parameters specifying source/drain junction area (`as`, `ad`) and perimeter (`ps`, `pd`), directly determining junction parasitic capacitances.

Parameters representing the number of diffusion squares in series with drain (`nrd`) and source (`nrs`), determining extrinsic source/drain parasitic sheet resistance.

A frequency division function where the fundamental frequency of the output signal is exactly half that of the input clock ($f_{out} = f_{in} / 2$).

Differential D-type latch stage comprising a differential sampling pair, a regenerative cross-coupled pair, clock gating switches, resistive loads, and a tail current device.

Physical verification process confirming that a layout geometry complies with all semiconductor foundry manufacturing constraints (widths, spacings, overlaps, enclosures).

The ratio of high-logic duration to total waveform period ($T_{high} / T_{period} \times 100\%$).

An analytical RC network delay approximation model that estimates signal propagation delay as the sum of resistances multiplied by the downstream downstream capacitances.

The critical project milestone where synthetic agent-generated baseline data and an empty 178-byte GDSII layout were identified, rejected, and replaced with verified Cadence simulation.

The number of standard logic gate inputs driven by a single output node, determining effective capacitive loading and signal transition slew rates.

A unit of electrical energy equal to $10^{-15}$ Joules ($1\text{ fJ} = 1\text{ mW} \times 1\text{ ps}$), commonly used to quantify power-delay product in nanoscale VLSI circuits.

A composite performance index that combines disparate circuit metrics (operating frequency, power consumption, area, phase error) into a single scalar value for cross-technology comparison.

A composite performance metric in frequency divider literature balancing operating frequency, power dissipation, and phase accuracy: $\text{FoM}_\phi = 10 \log_{10}[f_{in} / (P \cdot \Delta\phi_{max})]$.

A POSIX file advisory locking mechanism used on the host operating system to serialize access to shared hardware resources.

Dividing a wide transistor channel into multiple parallel narrower fingers sharing common source and drain diffusions to reduce gate resistance and diffusion capacitance.

The standard-threshold, 1.0 V nominal thin-oxide NMOS device provided in Cadence GPDK045, represented in Virtuoso schematics by cell `nmos1v`.

The non-silicided n-plus polysilicon resistor cell in Cadence GPDK045, featuring 3 electrical terminals (plus, minus, and substrate bulk tie).

The small-signal output conductance of a transistor ($g_{ds} = \partial I_{ds} / \partial V_{ds}$), representing the inverse of small-signal output channel resistance $r_o$.

Virtuoso Layout Suite XL command that automatically translates schematic instances and connectivity bindings into placed layout PCells and boundary pins.

The ratio of change in drain current to the change in gate-to-source voltage ($g_m = \partial I_{ds} / \partial V_{gs}$), measuring device amplification strength.

A mandatory review milestone between project stages where strict technical criteria must be fulfilled before committing time and VM resources to subsequent tasks.

Cadence Generic Process Design Kit for 45 nm CMOS technology, providing BSIM4 SPICE models, Virtuoso PCells, techfiles, and Assura verification rule decks.

The common reference potential node (0 V) in the circuit.

Lightweight, rapid AI worker agents deployed in background sessions to execute repetitive commands inside the Cadence VM.

Signal inversion logic function where logic high maps to low and vice versa.

Undesired short-term variations and phase fluctuations of the significant clock transition edges from their ideal positions in time.

A destructive low-impedance short-circuit path formed between power and ground rails by parasitic bipolar transistors (p-n-p-n SCR structures) in bulk CMOS.

Assura DRC rule in GPDK045 mandating that NMOS source/drain diffusions must reside within a specified proximity to a p-substrate tie tap.

Physical verification stage that compares extracted circuit connectivity from layout against the original schematic netlist to verify 1-to-1 equivalence.

Connectivity-aware layout environment in Cadence Virtuoso that maintains real-time binding with the schematic, enabling guided placement, flying wires, and DRC checking.

The total lumped capacitive load present at an output node, consisting of gate oxide capacitances, junction diffusion capacitances, and interconnect parasitics.

Passive pull-up resistive elements connected between the positive supply rail (VDD) and the differential output nodes (Q, Qb).

Differential NMOS transistor pair responsible for sensing input signals D and Db during the clock sampling phase.

Cross-coupled NMOS transistor pair providing positive regenerative feedback to latch and store logic states during hold phase.

Clock-controlled switch transistor activated when CK is high to connect the sampling pair M1–M2 to the tail node.

Clock-controlled switch transistor activated when complementary clock CKb is high to enable regenerative latching.

NMOS transistor connected between common tail node and ground, biased at gate voltage vb to establish total bias current.

Planar conductive aluminum/copper interconnect layers separated by dielectric insulating oxide in a CMOS process stack.

Assura DRC rule specifying that any polygon drawn on Metal1 must have a minimum planar surface area of at least $0.02\text{ }\mu\text{m}^2$.

The minimum load resistance required to establish a regenerative loop gain greater than unity ($g_m R_L > 1$) in a differential latch.

The drift velocity acquired by charge carriers (electrons in NMOS, holes in PMOS) per unit applied electric field: $v_d = \mu E$.

Named configuration blocks within SPICE model libraries defining statistical process corner variations for NMOS and PMOS transistors.

A statistical circuit simulation method evaluating parametric yield by randomly varying device model parameters according to foundry-measured statistical and mismatch distributions.

Metal-Oxide-Semiconductor Field-Effect Transistor, a voltage-controlled switching and amplifying device utilizing an insulated gate.

An electrical clock generation architecture that produces multiple periodic output signals possessing equal frequency but systematically staggered phase angles.

A parameter in Cadence schematic and SPICE netlists that instantiates multiple identical parallel copies of a transistor to scale total width.

A text-based description of circuit connectivity, device models, and parameter instances used by simulation and verification engines.

N-channel Metal-Oxide-Semiconductor field-effect transistor conducting electrons through an n-type inverted channel formed in a p-type substrate.

Cadence specialized SKILL-based command-line scripting language designed to automate simulation setup, batch execution, and waveform post-processing.

The peak-to-peak voltage differential between the minimum and maximum steady-state logic output levels ($V_{swing} = V_{max} - V_{min}$).

Direct port of Kuo et al.'s sizing rule ($m=1, R_1 = R_2 = R_{on}/2 = 1.15\text{ k}\Omega$) into GPDK045 at 1.4 GHz, which fails to divide.

Unwanted intrinsic capacitances formed by gate-to-channel overlap ($C_{gs}, C_{gd}$), channel-to-bulk ($C_{gb}$), and reverse-biased source/drain p-n junctions ($C_{sb}, C_{db}$).

A switching circuit arrangement using MOS transistors to pass or block bidirectional analog or digital signals under clock control.

A programmable Virtuoso layout or schematic generator whose geometric dimensions and terminal structures update dynamically based on CDF parameters.

A comprehensive package of device models, technology files, PCells, and verification rule decks provided by a foundry for designing ICs in a specific fabrication process.

The maximum absolute angular deviation of an actual output phase step from the ideal theoretical spacing of 45.0 degrees: $\Delta\phi_{max} = \max |\Delta\phi_i - 45^\circ|$.

The angular difference between consecutive output phases in an 8-phase frequency divider: $\alpha = 180 \times t_{pair} \times f_{in}$ degrees.

The geometrical polygon representation of semiconductor layers, diffusions, polysilicon gates, metal interconnects, and vias used to manufacture integrated circuits.

An IC layout stage containing positioned transistor cells, passives, and I/O boundary pins, but lacking detailed interconnect routing between terminals.

P-channel Metal-Oxide-Semiconductor field-effect transistor conducting positive charge carriers (holes) through an inverted p-type channel in an n-well.

Total electrical energy consumed per unit time by the circuit, calculated as average supply current multiplied by nominal supply voltage: $P = V_{DD} \times I_{avg}$.

Energy consumed per switching event, calculated as the product of total power dissipation and average propagation delay: $\text{PDP} = P_{avg} \times t_{pd}$.

A frozen, clean virtual machine disk state stored prior to batch simulation and routing experiments, allowing instant rollback in case of disk exhaustion or environment corruption.

Statistical fabrication process variations representing extreme speed boundaries for NMOS and PMOS devices: typical (tt), fast-fast (ff), slow-slow (ss), fast-slow (fs), slow-fast (sf).

The elapsed time between an input clock transition (50% level) and the corresponding transition at an output terminal.

Cadence binary simulation database format used by Spectre to store transient, DC, and AC simulation waveforms and operating point parameters.

Design characterization assessing circuit functionality and performance across variations in semiconductor manufacturing, supply rail, and ambient temperature.

Cadence next-generation parasitic extraction tool replacing older Assura RCX, extracting accurate 3D field-solver capacitances and resistances.

Text-formatted SPICE simulation output format containing structured simulation vectors, time steps, and nodal waveforms.

Automated physical verification step that calculates parasitic interconnect resistances (R), ground capacitances (C), and cross-coupling capacitances from layout geometries.

The active latching process in a digital latch where positive feedback from a cross-coupled pair amplifies a small differential input voltage into full rail-to-rail logic levels.

The fundamental design inequality derived in this project guaranteeing that the small-signal open-loop gain of the cross-coupled regenerative pair exceeds unity ($g_m R_1 > 1$).

The excess load resistance or loop gain beyond the critical oscillation threshold needed to ensure reliable latching across process, voltage, and temperature variations.

A formal, verifiable technical statement specifying a functional capability, performance target, or constraint, with an explicit acceptance criterion and evidence file.

A closed loop arrangement of logic elements where the output of each stage feeds the input of the subsequent stage, with an overall feedback loop inversion.

A formal project management record cataloging identified technical, security, and schedule risks, assessing likelihood and impact, and defining concrete triggers and mitigations.

Cadence configuration control file for Assura DRC, LVS, and RCX containing execution parameters, cell names, view targets, and rule set inclusions.

A foundry-supplied ASCII rule definition file specifying layer operations, geometric spacing rules, and electrical connectivity extraction statements for Assura.

The operational phase in a latch where input signals are actively tracked and transferred to intermediate internal nodes under clock control.

The MOSFET operational state where drain-to-source voltage exceeds saturation voltage ($V_{ds} \ge V_{dsat} = V_{gs} - V_{th}$), causing drain current to saturate and depend primarily on $V_{gs}$.

Virtuoso schematic verification utility that detects open pins, floating nets, short circuits, and naming conflicts before netlisting.

Spectre simulation executed directly from the Virtuoso schematic database using the Virtuoso netlister and OCEAN rather than a standalone hand-written netlist.

The autonomous oscillation frequency of a closed-loop divider when clock input amplitude is reduced to zero, caused by positive loop gain.

A transistor and load sizing strategy proposed by Kuo et al. setting unit NMOS width and designing load resistance to equal half of on-resistance ($R_1 = R_{on}/2$).

Cadence proprietary Lisp-like extension programming language used to automate and customize all operations across Virtuoso schematic, layout, and database editors.

Cadence flagship SPICE-class circuit simulator providing high-accuracy transient, RF, and reliability analysis for advanced nanometer nodes.

The effective series on-resistance of the three cascaded NMOS transistors in the DLATCH pull-down network (sampling device, clock switch, and tail transistor).

Assura DRC substrate connectivity error occurring when a diffusion layer touches a substrate or well without a valid physical tap contact or when multiple conflicting taps exist.

A headless Spectre netlist created for standalone simulation without opening Cadence Virtuoso, using default BSIM4 process parameters.

Mechanical stress exerted on transistor silicon active channels by surrounding Shallow Trench Isolation oxide, altering carrier mobility and threshold voltage based on distance to STI edge.

A multi-channel validation algorithm requiring all eight outputs of the divider to toggle at exactly half the input frequency ($f_{in} / 2 \pm 0.1\%$) with swing $\ge 0.1\text{ V}$.

A multi-agent engineering workflow distributing tasks between specialized LLM agents for VM execution, scripting, text auditing, and verification.

Heavily doped ohmic diffusion regions (p+ in p-substrate, n+ in n-well) that connect bulk silicon to ground (VSS) or power (VDD) to prevent latch-up.

The weak diffusion current flowing between drain and source of a MOSFET when gate voltage is below threshold ($V_{gs} < V_{th}$): $I_{sub} \propto \exp[(V_{gs} - V_{th}) / (n k_B T / q)]$.

Power supply voltage variations evaluated during PVT characterization, spanning $\pm 10\%$ around nominal 1.0 V supply.

The positive direct current electrical supply rail providing operating power to the integrated circuit.

A current-regulating element connected between the common-source node of a differential pair and ground, establishing total bias current.

Operating temperature extremes evaluated during environmental characterization: industrial cold ($-40^\circ\text{C}$), room nominal ($27^\circ\text{C}$), and junction hot ($125^\circ\text{C}$).

The minimum gate-to-source voltage required to invert the silicon surface and create a conducting channel between drain and source.

The property that enables any reported number, plot, or conclusion to be tracked directly to an underlying raw simulation log, netlist, and rerun script.

A structured comparative evaluation of alternative design choices against weighted technical feasibility, cost, headroom, and risk criteria.

The MOSFET operational state where drain-to-source voltage is smaller than saturation voltage ($V_{ds} < V_{dsat} = V_{gs} - V_{th}$), acting as a voltage-controlled linear resistor.

The continuous frequency span over which a circuit maintains correct operation, expressed in MHz/GHz or as percentage fractional bandwidth: 2 * (f_max - f_min) / (f_max + f_min) * 100%.

The working unit-device frequency divider circuit using $m = 1$ transistors and $8\text{ k}\Omega$ load resistors operating at 1.4 GHz.

The drain-to-source voltage at which electron velocity saturation occurs in short-channel MOSFETs, demarcating the boundary between triode and saturation regions.

A tabular cross-reference mapping each system requirement to its acceptance criterion, verification method (test, inspection, analysis), and specific evidence log path.

A conductive vertical metal plug etched through inter-layer dielectric oxide connecting two adjacent horizontal metal routing layers.

Type-2 hardware virtualization hypervisor hosted on the Linux workstation to run the legacy 32-bit CentOS 6.5 Cadence environment.

Cadence graphical waveform display and signal analysis environment embedded in Virtuoso for viewing transient, frequency, and eye diagram waveforms.

Assura hierarchical compiled database format that stores schematic netlist structures for direct comparison against extracted layouts during LVS.

The allowable DC voltage range across active transistors in a series stack before devices are forced into linear/triode operation or encounter supply rail limits.

Threshold voltage and mobility shifts in MOSFETs caused by scattered high-energy dopant ion scattering off photoresist edges during retrograde well implantation.