Multiphase Divide-by-Two CMOS Frequency Divider in Cadence GPDK045

In conventional multiphase dividers, generating 8 phases typically required 3 cascaded divide-by-two dividers driven by a 4-phase input clock (Kuo et al., Section I, p. 617). Here, four differential D-latches are connected in a closed ring with an overall feedback inversion (Q4 connected to D1b). A logic transition requires two full traversals of the 4-latch loop to return to its initial state, resulting in an output period exactly twice the input clock period (f_out = f_in / 2). Because each differential latch provides complementary true and inverted outputs, four physical latches naturally yield all eight evenly spaced phases (0°, 45°, 90°, ..., 315°) from a differential input clock without requiring LC components or extra divider stages.

Each DLATCH operates in two alternating phases controlled by complementary clocks CK and CKb. During the sampling phase (CK high), clock switch M5 is active, enabling the differential pair M1–M2 to steer bias current through load resistors R1 and R2 to track input voltages D and Db. During the hold phase (CKb high), switch M5 turns off and switch M6 turns on, activating the cross-coupled regenerative pair M3–M4. Positive feedback formed by cross-coupling M3 and M4 provides differential negative resistance (-2/gm), holding the sampled logic state and actively restoring differential voltage levels.

To allow signal propagation through a 4-latch ring without racing conditions, adjacent latches alternate between sampling and holding. Latches 1 and 4 sample on CK and hold on CKb, whereas latches 2 and 3 receive inverted clock connections (sampling on CKb and holding on CK). When CK is high, latch 1 samples input data while latch 2 holds its previous state; when CK falls, latch 1 transitions to hold, presenting stable outputs that latch 2 immediately samples. This master-slave handoff across the four stages prevents data from racing through multiple transparent latches in a single clock phase.

The inter-latch connections alternate between direct and swapped differential routing: Q1b connects to D2, Q2 connects to D3, Q3b connects to D4, and Q4 connects to D1b (with complementary connections to Db terminals). This structural alternation balances propagation delay across differential paths and ensures proper phase ordering around the ring. The final feedback inversion from Q4 to D1b provides the negative loop gain necessary for stable divide-by-two oscillation rather than locking into a static latch-up state.

Kuo et al. designed their circuit in 180 nm CMOS with a single pull-down discharging assumption, setting R1 = Ron/2. In 45 nm GPDK045, the pull-down path comprises a series stack of three active NMOS transistors (sampling transistor M1, clock switch M5, and tail current transistor M7), producing a total stack resistance of 3 Ron = 6.90 kΩ for unit devices (Ron = 2.3 kΩ). Regenerative latching requires small-signal loop gain gm*R1 > 1, establishing the stack regeneration condition R1 >= 1.1 * 3Ron/m = 7.59 kΩ for m = 1. The paper's value of 1.15 kΩ provides insufficient loop gain, causing the circuit to fail to latch and instead oscillate at 2799.8 MHz (2.0 * f_in) with an unviable 15.3 mV swing.

When an output node discharges, current flows through M1, M5, and M7 in series to ground. Each unit NMOS (W = 240 nm, L = 45 nm) presents channel on-resistance Ron = 2.3 kΩ, yielding total series resistance 3 Ron = 6.90 kΩ. Scaling the transistor multiplier to m = 4 places four identical channels in parallel, dividing the effective channel resistance by m: R_stack = 3 Ron / m = 6.90 kΩ / 4 = 1.725 kΩ. The required minimum load resistance scales correspondingly to R1 >= 1.1 * (3 Ron / 4) = 1.90 kΩ (tolerance band 1.88–2.25 kΩ). Choosing R1 = R2 = 3 kΩ in Design D provides comfortable margin above 1.90 kΩ, ensuring reliable regenerative latching across PVT corners.

In classic analog textbooks, tail transistor M7 is assumed to operate in saturation (Vds >= Vdsat) to act as a high-impedance current source. In 45 nm GPDK045 with nominal VDD = 1.0 V, three stacked NMOS devices must share the available voltage headroom. Transient simulation in Spectre extracts M7 drain voltage V(tail) between 8.1 mV and 66.9 mV (peak 68.2 mV on XD2), whereas extracted BSIM4 saturation voltage is Vdsat = 357.8 mV. Because Vds remains far below Vdsat, M7 operates deeply in the linear (triode) region, acting as a small degeneration resistor (~1.7 kΩ) rather than an ideal current source. This does not prevent division, but reduces common-mode rejection and couples supply variations directly into bias current.

According to the Elmore delay formulation in Kuo et al., total output capacitance at node Q1 is modeled as 8C (accounting for local diffusion capacitance, interconnect loading, and input capacitance of subsequent stages). During a falling transition, node Q1 discharges through the pull-down stack designed to present effective resistance R/2 = R1, giving propagation delay t_pdf = (8C)(R/2) = 4RC. During a rising transition, node Q1 charges from VDD through load resistor R1 = R/2, giving charging delay t_pdr = (8C)(R1) = (8C)(R/2) = 4RC. Because t_pdf = t_pdr = 4RC, output rise and fall times are theoretically equalized, ensuring 50% duty cycle and preventing edge-dependent phase distortion.

Applying the sizing concept scales transistor multiplier from m = 1 to m = 4 and reduces load resistance from 8 kΩ to 3 kΩ. Decreasing load resistance increases static DC current drawn from VDD during both sampling and holding phases according to I_avg ≈ VDD / (R_L + R_stack). Furthermore, quadrupling transistor sizes increases parasitic gate and diffusion capacitances by approximately 4x, elevating dynamic switching power (f * C * V^2). As a result, power increases by 3.94x (from 0.1375 mW to 0.5413 mW), which is the necessary physical trade-off to cut propagation delay by 2.39x (from 62.21 ps down to 25.99 ps) and expand operating bandwidth.

In this 4-latch architecture, outputs toggle in pairs separated by inter-pair delay t_pair, producing alternating phase steps of α = 180 * t_pair * f_in and (90° - α). Ideal 45° spacing occurs only when clock frequency satisfies f_in = 1 / (4 * t_pair). For Design D at 1.4 GHz, t_pair = 25.95 ps yields α = 6.54°, resulting in alternating steps of 83.46° and 6.54° (error = |83.46° - 45°| = 38.46°); its ideal 45° frequency is 9.63 GHz, far beyond its bandwidth. For Design B at 6.0 GHz, t_pair = 38.16 ps yields α = 41.22°, resulting in alternating steps of 48.78° and 41.22° (error = 3.78°), because 6.0 GHz operates very close to its ideal 45° frequency of 6.55 GHz.

Frequency division requires that each half-clock period accommodates the propagation delay through two latches: T_CK/2 > 2 Td. For Design B with R1 = 2 kΩ and C_L = 10 fF, the theoretical parasitic-free delay lower bound is Td >= R1 * C_L = 20 ps (2 Td >= 40 ps). At 6.0 GHz (T_CK/2 = 83.3 ps), the circuit divides cleanly, but actual measured single-edge CK-to-Q1 delay is 66.10 ps (3.3x the intrinsic RC bound) due to internal transistor junction and gate parasitics. At 6.25 GHz, T_CK/2 drops to 80.0 ps, leaving insufficient time for regeneration and signal settling, causing regenerative latching to fail.

Output voltage swing is determined by the RC charging and discharging time available during each clock phase. At 1.4 GHz (half-period 357 ps), output nodes have ample time to charge through load resistor R1 toward VDD and discharge through the stack toward ground, achieving a wide differential swing of 0.4344 V (0.583 V to 1.017 V). At 6.0 GHz, the clock half-period shrinks to only 83.3 ps, which is comparable to the circuit time constant (tau = R_L * C_L ≈ 20–30 ps). The output transitions are truncated before reaching their asymptotic voltage rails, reducing peak-to-peak swing to 0.1349 V (0.818 V to 0.953 V), just above our strict 0.1 V threshold.

Design D was characterized across a 45-corner matrix (5 process corners x 3 temperatures x 3 supplies). Exactly 41 of 45 corners passed (91.1% yield). All 4 failures occurred exclusively at the extreme high-temperature (125 °C) and low-supply (0.9 V) condition across corners tt, ss, fs, and sf. At 125 °C, carrier mobility drops due to increased phonon scattering while subthreshold leakage rises; combined with reduced supply headroom (0.9 V), pull-down drive current degrades significantly. For tt, ss, and sf corners at 125 °C / 0.9 V, outputs failed to divide (ratio 0.5001, oscillating at 2*f_in); for fs at 125 °C / 0.9 V, the circuit divided but output swing dropped to 0.093 V, narrowly failing our strict 0.100 V swing criterion.

Design B is aggressively sized for maximum speed (6.0 GHz) with smaller load resistors (R1 = 2 kΩ), placing it right at the margin of the regeneration requirement (R_crit = 1.90 kΩ). At 6.0 GHz, the timing budget is extremely tight (half-period 83.3 ps). Elevated temperature (125 °C) degrades electron mobility by ~35% and increases stack resistance, pushing effective loop gain below unity and slowing transition times beyond the 83.3 ps window. Consequently, all 15 corners at 125 °C fail to divide (0/15). Design B operates reliably across cold (-40 °C: 13/15 pass) and room temperature (27 °C: 8/15 pass), but lacks the thermal headroom of Design D.

In GPDK045, standard-Vt thin-oxide transistors (`g45n1svt` / `nmos1v`) are rated for a nominal operating voltage of 1.0 V, with an absolute maximum recommended voltage parameter `max_vdd_1v = 1.1 V`. Setting nominal VDD at 1.0 V allows standard ±10% industrial voltage tolerance sweeps (0.9 V to 1.1 V) where the upper corner lands exactly on the foundry reliability limit. If 1.1 V were chosen as nominal, a +10% corner would reach 1.21 V, exceeding the gate oxide breakdown rating and inducing hot-carrier degradation.

Initial sweep implementations checked frequency solely on output node Q1 using zero-crossing detectors, which erroneously counted false passes when the circuit failed to divide and instead produced low-amplitude harmonic oscillations at 2 * f_in (2.8 GHz). To eliminate false passes, we instituted a strict multi-channel verification routine in `measure_guest.py`: all eight output nodes (q1, q2, q3, q4, q1b, q2b, q3b, q4b) must toggle at exactly f_in/2 within 0.1% tolerance, and every output must sustain peak-to-peak voltage swing >= 0.100 V across at least 15 steady-state cycles.

Physical layout development was executed systematically within the available project timeline: unit NMOS PCells and polysilicon load resistors were instantiated and placed in Cadence Virtuoso via SKILL (`build_layout_v2.il`), establishing valid bounding boxes and pin terminals for DLATCH and divider_core. Automated routing was attempted using Layout XL and the Chip Assembly Router (vcar), but produced 134 DRC violations and an open net. To adhere strictly to scientific honesty in our defense report, we elected to report the clean placement layout with its audited 21 DRC violations rather than claiming a completed routed layout that does not pass LVS.

Running Assura DRC on cell view `divider_lib/DLATCH/layout` against `assuraDRC.rul` generated exactly 21 real errors across 3 distinct design rules: Rule 220 (`psubstrate_StampErrorMult`) produced 1 error because substrate connections formed multiple conflicting stamp potentials; Rule 221 (`psubstrate_StampErrorConnect`) produced 6 errors where NMOS source/drain taps lacked explicit ohmic ties to substrate ground; and Rule 595 (`METAL1.A.1`) produced 14 errors because metal pads on cell I/O pins had planar areas smaller than the required foundry minimum of 0.02 μm^2.

We exported `DLATCH` from Layout XL (`layout_lxl`) with 28 NMOS instances and 9 pins, and executed batch autorouting via `vcar` (`route_dlatch.il`). The router completed global and track routing for 136 of 137 connections (99.27% completion), inserting 37 vias and 217 shapes. However, detail routing left 1 open connection on internal net `xs` (0.115 μm gap between M5 drain and M2 source). Running Assura DRC on `layout_routed` revealed 134 real errors across 17 rules, predominantly `LATCHUP.2` substrate tap proximity (56 errors) and `NIMP.O.1` implant overlaps (21 errors), because the router placed metal without respecting custom analog guard-ring rules.

Assura LVS failed due to two fundamental discrepancies: first, the unrouted net `xs` caused an electrical open; second, schematic load resistors were instantiated from `analogLib/res` (2-terminal ideal devices), whereas Layout XL placed GPDK045 `g45rnsnp` polysilicon resistors, which possess a 3rd physical substrate bulk tie terminal. Furthermore, automated parasitic extraction (RCX / QRC) was completely blocked because the university GPDK045 PDK distribution lacked the required Quantus QRC technology rule directory (`qrcSetupDir qrc` is absent). Consequently, post-layout simulation could not be executed.

Simulating Design D at 1.4 GHz using the standalone netlist yielded 0.5413 mW power and 25.99 ps delay, while simulating the Virtuoso testbench directly via OCEAN yielded 0.4554 mW power and 26.66 ps delay (a 15.9% power drop). Through a controlled experiment (`power_gap_experiment.md`), we discovered that the Virtuoso netlister automatically calculates and injects layout-dependent BSIM4 stress, proximity, and parasitic parameters into every device: `sa=140n sb=140n sd=160n sca=226.0 scb=0.117 scc=0.028 nrd=1.167 nrs=1.167`. When these exact parameters were appended to the standalone netlist, power shifted to 0.455402 mW (matching OCEAN to within 0.02%), proving that mechanical STI stress and well proximity reduce carrier mobility and drive current.

Writing automated batch SKILL scripts required overcoming several subtle Cadence IC615 environment quirks: first, SKILL uses dynamic variable scoping, and the PDK's `libInit.il` overwrote global variable `y` upon initialization, requiring all coordinate variables to be renamed `v2y` and warming up the PDK before execution; second, Lisp-style conditional clauses `((null(x)) ...)` were misparsed as function calls to x, requiring syntax `(null(x) ...)`; third, `schCreateWireLabel` required a strict 9-argument form ending with `nil` to successfully commit wire names; and fourth, setting CDF parameters had to precede wire connections to prevent PDK callbacks from regenerating device symbols and disconnecting nets.

Because the legacy Cadence tools run inside a headless VirtualBox VM without network sharing, host scripts communicate via a virtual serial port (`/dev/ttyS0`). The host injects shell commands into the guest using `VBoxManage controlvm CadenceVM keyboardputstring`, and monitors host file `serial.txt` until a unique completion token (`echo __DONE_$n > /dev/ttyS0`) appears. Large scripts and RSF templates are packaged dynamically into temporary ISO9660 filesystems via `xorriso` and attached to the virtual CD-ROM drive (`/mnt/r`). Concurrency across background subagents is strictly serialized using POSIX file lock `flock vm.lock`.

Running `schCheck` on `tb_divider` yields 0 errors and exactly 1 warning: `Warning: Instance name collides with signal name - "VDD"`. This occurs because the DC supply voltage source instance is named `VDD` while being connected to supply net `VDD`. Renaming the instance in the schematic would alter instance naming in extracted netlists and break compatibility with external measurement scripts that reference `V(VDD:p)`. Because this warning is a benign naming notice that does not affect electrical connectivity or simulation accuracy, it was intentionally preserved and documented.

In initial project commits (d346d36 through 38aa969), an autonomous AI agent swarm generated unverified, fabricated deliverables, including hardcoded simulation tables and an empty 178-byte GDSII layout file falsely claiming '0 DRC errors'. Upon discovering these synthetic files (commit a805b27), we rejected all unverified artifacts, acknowledged the failure, and rebuilt the repository from first principles. We instituted a real Cadence Virtuoso IC615, Spectre 12.1, and Assura 4.1 verification flow inside a CentOS VM, requiring all reported numbers to originate from traceable raw simulation logs and real SKILL-generated layouts.

We utilized a coordinated workflow where routine, high-volume tasks (such as executing headless VM commands, monitoring serial logs, and extracting PVT TSV rows) were delegated to fast worker agents, while advanced models assisted with derivations and script generation. To prevent AI hallucinations and promotional phrasing, we enforced independent multi-stage audit rounds: a Quantitative Numbers Audit (`REVIEW3_numbers.md`) that verified every single number against disk logs, an Academic Prose Audit (`REVIEW3_prose.md`) that purged promotional padding, and visual review passes.

First, I would perform manual routing of the DLATCH cell by placing Metal1/Metal2 interconnects on standard grids, placing dedicated substrate tap guard-rings to eliminate the 56 LATCHUP.2 errors, and instantiating 3-terminal `g45rnsnp` poly resistors with proper bulk ties. Second, I would obtain the missing foundry Quantus QRC technology rule files for GPDK045 to perform parasitic RC extraction (RCX). Third, I would execute post-layout transient and PVT simulations on the extracted view (`av_extracted`) to quantify the exact delay degradation and phase error shifts introduced by physical wiring parasitics.

Compared to Kuo et al.'s 180 nm design (VDD = 1.8 V, 2.34 mW power at 1.4 GHz), our 45 nm GPDK045 Design D achieves a 4.3x reduction in power (0.541 mW at 1.0 V supply) while operating at the same 1.4 GHz clock with 91.1% PVT yield (41/45 pass). Furthermore, our high-speed Design B scales operation up to 6.0 GHz with 0.493 mW power, achieving a maximum phase-step error of 3.78°, which matches Kuo et al.'s reported 3.75° benchmark while operating at 4.3x higher frequency and consuming 79% less power.

Following v2/PLAN.md, our immediate next step is executing Stage S0 decisions (enhancement path, venue, and QRC file pursuit), re-baselining nominal runs under the VM lock, and launching the recommended E1 sizing exploration (sweeping multiplier m from 2 to 8 and load R from 1 to 8 kΩ at 1.4 and 6.0 GHz) alongside E6 bias trim. This maps the f_max and phase error boundaries to select optimal Design D and Design B successors. Concurrently, we will manually route DLATCH m=4 R=3k to reduce DRC errors and shrink LVS mismatches, and draft the manuscript strictly enforced by a claims register. If E1 yields insufficient gain, we fall back to publishing an empirical correction letter documenting the 45 nm breakdown of the paper rule.

In 45 nm GPDK045 under a 1.0 V supply, voltage headroom is severely constrained. Operating point extraction demonstrates that M7 drain voltage Vds is only 8 to 68 mV, while BSIM4 saturation voltage Vdsat is 357.8 mV. A regulated cascode stack requires roughly 2 * Vdsat plus margin (approx. 700 mV), which cannot fit under a 1.0 V rail alongside the two switching and sampling NMOS levels and the load resistor IR drop. Furthermore, inserting cascode devices adds parasitic capacitance at the common-source nodes (xs and xh), degrading high-frequency bandwidth without resolving the fundamental stack regeneration requirement. In our trade study (v2/TRADE_STUDY.md), the cascode option scored lowest (18/60) and was rejected.

We enforce an institutional Claims Register rule set (v2/CLAIMS_AUDIT.md and SR-09). Rule 1 dictates that no numerical metric enters the manuscript without an explicit evidence file path in results/ or report/ and a verified, rerunnable Spectre/Assura execution command. Rule 2 requires that figure captions cite the exact simulation corner and file. Rule 3 mandates reporting the netlist variant (standalone vs schematic CDF parameters) and measurement window for power. Rule 5 strictly forbids corner hiding by requiring full disclosure of all 45 PVT corners with failure reasons. Finally, an automated claims audit script cross-examines draft text against simulation logs before manuscript submission.

An audit of the early v2 draft (v2/CLAIMS_AUDIT.md) revealed that its headline numbers were never simulated in Cadence Spectre and directly contradicted our measured 45 nm results. The early draft claimed a 1.8 V supply (v1 is 1.0 V), 180 nm device sizes (v1 is 45 nm), 2.2 mW power dissipation, 800 mV swing, a 0.5° dynamic phase interpolator, and active PMOS loads peaking to 3.2 GHz. None of these circuits existed in the repository, and several violate physical headroom constraints at 1.0 V. Carrying forward unverified or contradicted figures violates scientific integrity, so the early draft was retired to legacy_draft/ and must be rewritten from first principles using traceable evidence.